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Browse Prior Art Database

Channel To Channel Adapter for Linking Two Data Processors

IP.com Disclosure Number: IPCOM000086229D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Mitchell, MJ: AUTHOR [+2]

Abstract

A mechanism is described for speeding up processor-to-processor data transfer operations and reducing the amount of software overhead in a system employing a channel-to-channel adapter. This is accomplished by utilizing unique addresses which are passed from one processor to the other by the adapter, and which immediately tell the receiving processor what is expected of it.

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Channel To Channel Adapter for Linking Two Data Processors

A mechanism is described for speeding up processor-to-processor data transfer operations and reducing the amount of software overhead in a system employing a channel-to-channel adapter. This is accomplished by utilizing unique addresses which are passed from one processor to the other by the adapter, and which immediately tell the receiving processor what is expected of it.

The drawing shows the hardware which is used in both an existing system and the improved system described herein. Data moves between the two processors when a write command is issued by the processor on one side of the channel-to-channel adapter and a read command is issued by the processor on the other side of the adapter. The direction of data transfer is from the processor issuing the write command to the processor issuing the read command.

In the existing system, if processor No. 1, for example, issues a write command, the adapter accepts and retains the command and then sends an attention status signal to the second processor for interruption thereof. Processor No. 2 then issues a sense command to the adapter which causes the adapter to send to processor No. 2 the command byte issued (and pending) by processor No. 1. The processor No. 2 program then examines the command byte to determine whether a read or a write command should be issued. Processor No. 2 then issues the proper complementing read command to the adapter and the transfer of data commences. The same procedure in reverse is followed when processor No. 2 issues a write command.

The mechanism described herein eliminates the need for the issuance of the sense command by and the passing of the command byte to the second or noninitiating processor. This is accomplished by enabling each processor to use certain unique device addresses for addressing the channel-to-channel adapter, and by enabling the adapter to pass the unique address from the initiating processor to the recipient processor at the time of issuance of the initial attention status signal.

A first unique device address, for example, "0A", is issued by the initiator processor when data is to be transferred from processor No. 1 to processor No. 2 and a second unique device address, for example, "0B", is issued when data is to be transferred in the opposite direction, namely, from processor No. 2 to processor N...