Browse Prior Art Database

Processor To Processor Communications Mechanism

IP.com Disclosure Number: IPCOM000086230D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 57K

Publishing Venue

IBM

Related People

Mitchell, MJ: AUTHOR [+2]

Abstract

A high-performance processor-to-processor communications mechanism is described for speeding up processor-to-processor data transfer operations, in a system employing a channel-to-channel adapter as the communications link. This is accomplished by: (1) providing multiple device addresses for the adapter to permit direction of transfer implication via software protocol; and (2) taking advantage of the block multiplexer channel disconnected command chaining capability, to hold pending channel programs on one processor which can be actuated when the other processor issues a corresponding initiating command.

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Processor To Processor Communications Mechanism

A high-performance processor-to-processor communications mechanism is described for speeding up processor-to-processor data transfer operations, in a system employing a channel-to-channel adapter as the communications link. This is accomplished by: (1) providing multiple device addresses for the adapter to permit direction of transfer implication via software protocol; and (2) taking advantage of the block multiplexer channel disconnected command chaining capability, to hold pending channel programs on one processor which can be actuated when the other processor issues a corresponding initiating command.

The hardware shown in the upper portion of the drawing describes a known type of processor-to-processor communications system, and the chart shown below the hardware describes the new mechanism for improving the performance of the system represented by the known hardware. For both the known system and the new mechanism, data moves between the two processors when a write command is issued by the processor on one side of the channel-to- channel adapter and a read command is issued by the processor on the other side of the adapter. The direction of data transfer is from the processor issuing the write command to the processor issuing the read command.

The method presently used in the known system will be briefly described for the example of a processor No. 1 to processor No. 2 data transfer initiated by processor No. 1. In this case, processor No. 1 issues a write command to the channel-to-channel adapter. The adapter accepts and retains the command and then sends an attention status signal to processor No. 2 for interruption thereof. Processor No. 2 then issues a sense command to the adapter which causes the adapter to send to processor No. 2 the command byte issued by processor No.
1. The appropriate channel program in processor No. 2 then examines the command byte to determine whether a read or a write command should be issued. Processor No. 2 then issues the proper complementing read command to the adapter and the transfer of data commences. The same procedure in reverse is followed when processor No. 2 issues a write command.

The mechanism described herein eliminates the need for the attention interruption, the issuance of the sense command by the recipient processor and the passing of the command byte to the recipient processor. This greatly reduces the operating overhead previously associated with the movement of data between the two processors.

As indicated by the chart in the drawing, there are four possibilities with respect to the direction of data transfer and the processor initiating the transfer. These are: (0A) Data transfer from processor No. 1 to processor No. 2 initiated by processor No. 2. (0B) Data transfer from processor No. 2 to processor No. 1 initiated by processor No. 2; (0C) Data transfer from processor No. 1 to processor No. 2 initiated by processor No. 1; (0D...