Browse Prior Art Database

Diagnostic Parity Error Forcing Mechanism

IP.com Disclosure Number: IPCOM000086231D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Kobesky, LJ: AUTHOR

Abstract

A hardware mechanism is described for testing parity checking circuits in a data processor for verifying that they are functioning properly. This mechanism includes exclusive OR circuitry associated with each parity generator in the processor, for deliberately forcing a bad parity bit when it is desired to perform the diagnostic testing of the parity checking circuit located downstream of the parity generator.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 84% of the total text.

Page 1 of 2

Diagnostic Parity Error Forcing Mechanism

A hardware mechanism is described for testing parity checking circuits in a data processor for verifying that they are functioning properly. This mechanism includes exclusive OR circuitry associated with each parity generator in the processor, for deliberately forcing a bad parity bit when it is desired to perform the diagnostic testing of the parity checking circuit located downstream of the parity generator.

The drawing shows a typical parity generator 10 and the exclusive OR circuitry associated therewith, this latter circuitry being comprised of NAND circuits 11, 12 and 13. During normal data processing operations, a test latch 14 is set to the "good" state. This enables NAND circuit 12 and disables NAND circuit 13. This allows the parity bit value on the parity output line 15 to be the same as that produced by the parity generator 10.

When it is desired to perform the diagnostic test of the parity checking circuit located downstream of the apparatus shown in the drawing, the test latch 14 is set to the "bad" state. This disables NAND circuit 12 and enables NAND circuit
13. This causes the parity bit value on the parity output line 15 to be the opposite of that produced by the parity generator 10. As a consequence, the parity bit value on output line 15 is wrong or bad. This causes the parity checking circuit to produce an error signal which, in turn, indicates that such parity checking circuit is functioning properly...