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Porous Process for Electrical Feedthrough in Silicon Wafers Used for Modules

IP.com Disclosure Number: IPCOM000086260D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Aboaf, JS: AUTHOR [+2]

Abstract

Electrical feedthrough in silicon wafers used for modules can be fabricated using the following steps: opening holes from both sides of a silicon wafer; oxidizing the surface of the wafer: depositing metal layers on the wafer; subetching the metal films to form pads; placing pins on top of the pads and reflowing the metal to join the pads to the pins.

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Porous Process for Electrical Feedthrough in Silicon Wafers Used for Modules

Electrical feedthrough in silicon wafers used for modules can be fabricated using the following steps: opening holes from both sides of a silicon wafer; oxidizing the surface of the wafer: depositing metal layers on the wafer; subetching the metal films to form pads; placing pins on top of the pads and reflowing the metal to join the pads to the pins.

In this process, the thickness of the oxide is about one micron. Very thick thermal oxides are difficult to grow, but are necessary for the silicon modules to reduce capacitance and crosstalk between pins. Porous silicon can be used in this application as porous oxide thick layers have a low-dielectric constant.

In order to obtain a very low capacitance, a thick oxide and a low-dielectric constant are important. This necessitates a porous silicon of 80 to 90% porosity.

A two step process is useful to produce this high porosity and mechanical strength.

A porous film of about 1 to 2.5 microns thick of about 50-60% porosity is formed by anodization in HF (concentration 10%) and 20-30 mA/cm/2/.

A porous film of 10-20 microns thick of 80-90% porosity is grown by the same process but at high-current density (45-60 mA/cm/2/). This layer occurs under the first layer if p+ wafers are used.

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