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Fabrication of Integrated Circuits Incorporating High Performance Bipolar Transistors

IP.com Disclosure Number: IPCOM000086263D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 68K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A process is described for fabricating integrated circuits consisting of bipolar transistors. The resulting bipolar transistors have high gain and fast switching characteristics and, further, they occupy a small substrate area. Resistors and Schottky barrier diodes can be fabricated simultaneously with the bipolar transistors.

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Fabrication of Integrated Circuits Incorporating High Performance Bipolar Transistors

A process is described for fabricating integrated circuits consisting of bipolar transistors. The resulting bipolar transistors have high gain and fast switching characteristics and, further, they occupy a small substrate area. Resistors and Schottky barrier diodes can be fabricated simultaneously with the bipolar transistors.

The process, described sequentially, is as follows:

1. Start with a P type silicon wafer 2 of resistivity on the order of 10 to 20 ohm-cm.

2. Grow thermal silicon dioxide, typically 3500 Angstroms in thickness.

3. Using conventional photoresist technique and an appropriate mask, etch the silicon dioxide selectively.

4. Diffuse in an N-type impurity 4 of high concentration level, typically 5 x 10/2/atoms/cc at the surface of exposed silicon regions.

5. Grow thermal silicon dioxide, typically 4800 Angstroms in thickness. (The N-type impurity is simultaneously driven in.)

6. Using a photoresist technique and an appropriate mask, etch the silicon dioxide selectively.

7. Diffuse in a P-type impurity 6 of high concentration level, typically 5 x 10/20/atoms/cc at the surface of exposed silicon regions.

8. Etch away all silicon dioxide.

9. Grow, epitaxially, monocrystalline silicon 8, typically 2 mu m in thickness and doped, during the epitaxial growth, with an N-type impurity of low concentration level 6in the neighborhood of 2 x 10/16/ atoms/cc.

10. Diffuse in an N-type impurity 10 of high concentration level, typically 5 x 10/20/atoms/cc at the surface of the epitaxially grown silicon.

11. Grow thermal silicon dioxide 12 about 2000 Angstroms in thickness.

12. Using a photoresist technique and an appropriate mask, etch the silicon dioxide selectively. The cross section of the silicon wafer at the site of a bipolar transistor, as processed through sequential steps 1-12 is shown in Fig. 1.

13. Etch exposed silicon to a depth of about 8000 Angstroms. The technique of reactive ion etching is preferable for this silicon etching since it provides to the silicon "mesas", vertical sidewalls, or even sidewalls with a slight slope, if so desired, as shown in Fig. 8.

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14. Etch away all silicon dioxide.

15. Grow thermal silicon dioxide 14 about 150 Angstroms in thickness.

16. Deposit a layer of silicon nitride 16 typically 1000 Angstroms thick. The technique of sputtering silicon nitride using a point source is preferable for this silicon nitride deposition; for it will ensure the desired discontinuity of the silicon nitride layer along the sidewalls of the silicon mesas.

17. Using a photoresist technique and an appropriate mask, etch the silicon nitride selectively through reactive ion etching. Conventional chemical etching using hot phosphoric acid may be used in place of reactive ion etching. However, a ~ 1000 Angstrom layer of pyrolytic silicon dioxide must be deposited in that case immediately after the deposition of silico...