Browse Prior Art Database

Early Write Disconnect

IP.com Disclosure Number: IPCOM000086264D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

In an electronic data processing system of the type where a basic storage module 10 interfaces with a processor 12, such that the processor awaits the completion of store operations in the storage module 10 prior to commencing subsequent operations, the present technique permits the processor to commence subsequent operations prior to the storage cycle being completed in storage module 10.

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Early Write Disconnect

In an electronic data processing system of the type where a basic storage module 10 interfaces with a processor 12, such that the processor awaits the completion of store operations in the storage module 10 prior to commencing subsequent operations, the present technique permits the processor to commence subsequent operations prior to the storage cycle being completed in storage module 10.

The figure illustrates processor 12 interfacing a basic storage module 10, which is shown with some basic logic blocks usually found together with the memory arrays. The interface lines include the address bus entering latch L1 of the storage address register (SAR). The read (RD) and write (WRT) lines enter the control and timing logic of the basic storage module 10. The data bus interconnects the processor 12 with the error correcting code (ECC) logic. In the event an error is detected, this is transmitted to the processor 12 by the error line(s).

The acknowledge (Data RDY) line from the control and timing logic to the processor 12 is the critical line which releases the processor to perform subsequent operations. Previously, this line would transmit a ready signal to processor 12 only after a store operation had been completed. By the present technique, a ready signal is transmitted to the processor 12 at an earlier point in time speeding up the overall operation.

The data bus connecting processor 12 with the ECC logic normally carries half-words of inf...