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Error Detection in Registers Where Parity Checking is Unavailable

IP.com Disclosure Number: IPCOM000086265D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

DiPilato, NM: AUTHOR [+2]

Abstract

This is a technique for checking data in a special register on a real-time basis where parity checking is not available.

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Error Detection in Registers Where Parity Checking is Unavailable

This is a technique for checking data in a special register on a real-time basis where parity checking is not available.

The figure illustrates a system operating under the control of a read-only store (ROS). Data transferred from the general purpose registers to the special register is also written into the C register, shown as part of the arithmetic logic unit (ALU). Data is then read from the special register into the D register also located in the ALU.

The contents of the C register and the D register are compared by an exclusive OR circuit, for example, located in the ALU. The output of the exclusive OR circuit provides an error signal if the contents of the C register and the D register are not the same. In this manner, the contents of the special register is checked on a real-time basis without the availability of parity checking bits.

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