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Browse Prior Art Database

Enhancement Depletion Mode Field Effect Transistor Driver

IP.com Disclosure Number: IPCOM000086266D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Knepper, RW: AUTHOR

Abstract

This is an improved field-effect transistor (FET) driver circuit including both enhancement and depletion mode field-effect transistor devices, particularly useful when driving large fan-out and high capacity.

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This is the abbreviated version, containing approximately 77% of the total text.

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Enhancement Depletion Mode Field Effect Transistor Driver

This is an improved field-effect transistor (FET) driver circuit including both enhancement and depletion mode field-effect transistor devices, particularly useful when driving large fan-out and high capacity.

The present technique illustrates two circuits that use depletion mode devices as active switching devices. In Fig. 1, transistors T1 and T3 are depletion mode devices while T2, T4, T5 and T6 are enhancement mode devices. Transistor T5 is driven by a standard enhancement/depletion mode inverter including transistors T1 and T2. Transistor T6, however, as driven by a depletion mode device T3, that is itself driven by the input signal V/IN.

Transistor T4 is used to discharge node 2 when V/IN is down and is driven by the output of the inverter including transistors T1 and T2. The driver is an inverting circuit. Transistor T3 buffers the large gate capacitance of transistor T6 from the V/IN. The advantage of using T3 as a depletion device in a driven 'switched' mode is that T6 now receives a full VH drive voltage. Also node 2 is charged quite rapidly because T3 turns on hard when V/IN comes up. Device T6 can thus maintain a much lower downlevel and can therefore sink a larger current, allowing greater fan-out.

The circuit of Fig. 2 is similar to that of Fig. 1, except that it is a noninverting driver with some improvement in the balance between rise and fall time over the circuit of Fig. 1. Device T5 is h...