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Clamped Open Collector Driver

IP.com Disclosure Number: IPCOM000086267D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Reedy, DC: AUTHOR

Abstract

This is a transistor transistor logic (TTL) circuit in which the most positive uplevel of an open-collector output is limited.

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Clamped Open Collector Driver

This is a transistor transistor logic (TTL) circuit in which the most positive uplevel of an open-collector output is limited.

Open-collector drivers are required in TTL technologies to perform the collector DOT function. In such an open-collector configuration, it is possible to have a most positive uplevel that will adversely effect the driven transistors in subsequent stages.

The circuit of Fig. 1 minimizes the most positive uplevel at the output pin without impacting the least positive uplevel or the collector DOT capability of the circuit. Diodes D1, D2 and D3 together with the base-to-emitter diode drop of transistor T2 limit the most positive uplevel. The remainder of the circuit is conventional in TTL technologies.

If two inputs are desired, the circuit of Fig. 2 performs a similar limiting function by diodes D1, D2 and D3, together with the base-to-emitter diode drop of transistor T4. The clamped open-collector driver has the inherent advantage of a faster turn on delay than the conventional open collector, due to the smaller output signal swing. The smaller output signal swing also minimizes the magnitude of coupled noise that can be induced in the various wiring channels.

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