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Browse Prior Art Database

Wafer Deceleration for Orientation

IP.com Disclosure Number: IPCOM000086273D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Gruber, LW: AUTHOR

Abstract

Shown is a system for wafer orientation in in-line throughput or transfer point air track operation of semiconductor wafers.

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Wafer Deceleration for Orientation

Shown is a system for wafer orientation in in-line throughput or transfer point air track operation of semiconductor wafers.

In operation, wafer 10 flow on an air track network is dampened and checked at gate No. I with a control port 1, which when restricted by an overlying wafer, will provide a feedback signal to an upstream gating point in the air track network.

The gating unit, as shown in Fig. 2, includes two air bearing sleeve/pin combinations 2 that are positioned on each side or the air track. Cross drilled air jets 4, with a constant air flow, are aimed so that the air bearing sleeve 2 is projected angularly towards the center of track 6, with excess air bled through a vent 20. The travelling wafer 10 will, as it approaches, cover control port 1 between air bearing sleeves 2. The wafer 10 will be retained at the station until down stream controls (e.g., 12A, 12B and 12C) indicate a clear track for wafer travel. On a send signal, control vent 21 is opened, dumping air from within the bearings, permitting them to open and release the wafer 10.

These air bearing sleeves 2 are formed of thin-walled plastic cylinders, each trapped by small bored protruding diameter pins. The pins are cross drilled so that ported air can be directed against the inner wall of the sleeves in a desired direction to form the gate.

On release of the wafer 10, it travels onto a platform area 30 in the form of a conventional air track section, until...