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Reduction of Wafer Edge Effects in a Sputter Machine Under High Resputtering Conditions

IP.com Disclosure Number: IPCOM000086289D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Carlier, C: AUTHOR [+2]

Abstract

The high-resputtering rates needed to partially planarize a sputtered quartz deposition over narrow metal lands, deteriorate the thickness uniformity of the film across each wafer. The wafer edge effect responsible for this phenomena can be noticeably reduced by filling the empty spaces that surround each wafer on the anode plate. This can be achieved by using pieces of blank silicon P- < 111 > wafers.

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Reduction of Wafer Edge Effects in a Sputter Machine Under High Resputtering Conditions

The high-resputtering rates needed to partially planarize a sputtered quartz deposition over narrow metal lands, deteriorate the thickness uniformity of the film across each wafer. The wafer edge effect responsible for this phenomena can be noticeably reduced by filling the empty spaces that surround each wafer on the anode plate. This can be achieved by using pieces of blank silicon P- < 111 > wafers.

Planarized sputtered quartz is used to allow the etching of nonoverlap via holes. To achieve this type of via hole all over the surface of each product wafer, it is necessary to obtain a thickness uniformity of the film across each wafer. Under these conditions. the distortion of the electric field around each wafer in the anode dark space results in important variations of the resputtering conditions between the center and the periphery of each wafer. This, in turn results in a nonuniform film thickness across each wafer.

To reduce this wafer edge effect, the empty spaces that surround each wafer
(A) are filled in order to make the anode plate as flat as possible. Pieces of blank Si P- < 111 > wafers (B) are used for that purpose. Experiments have shown that the thickness difference between the center and the periphery of each wafer is then divided by two.

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