Browse Prior Art Database

Frame Synchronization

IP.com Disclosure Number: IPCOM000086291D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 21K

Publishing Venue

IBM

Related People

Vautier, R: AUTHOR

Abstract

For PCM systems, the CCITT recommends a frame synchronization procedure which is based on recognition of a fixed pattern in the first slot of the frame. For in-plant installation, this technique can be replaced by the proposed order variation to achieve a fast and very low cost synchronization of the frame.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Frame Synchronization

For PCM systems, the CCITT recommends a frame synchronization procedure which is based on recognition of a fixed pattern in the first slot of the frame. For in-plant installation, this technique can be replaced by the proposed order variation to achieve a fast and very low cost synchronization of the frame.

The data bits are transmitted with bipolar HDB 1 code in which sequences of two "0" bits are filled by OV (where V is a viol in the normal bipolar sequence) or by 1 V, depending on the number of transmitted "1's" between two viols.

The proposed frame synchronization pattern is based on a fixed pattern (see the drawing) composed of three 0 bits which are between two 1 bits. In this way three 0 bits are detected in the receiver as the synchro pattern. The synchro pattern cannot be imitated in the data stream because of the HDB 1 code.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]