Browse Prior Art Database

Redundancy Scheme for Array Chips

IP.com Disclosure Number: IPCOM000086293D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Haist, F: AUTHOR [+2]

Abstract

To increase the yield of highly integrated storage chips, redundancy schemes have been proposed, whereby additional storage bits or bit lines are arranged on one chip. The present redundancy scheme for highly integrated storage chips in multilayer design uses this concept, in that more logic circuits or storage cells are arranged on the chip than are actually required.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 1

Redundancy Scheme for Array Chips

To increase the yield of highly integrated storage chips, redundancy schemes have been proposed, whereby additional storage bits or bit lines are arranged on one chip. The present redundancy scheme for highly integrated storage chips in multilayer design uses this concept, in that more logic circuits or storage cells are arranged on the chip than are actually required.

The chip layout is such that the storage matrix or a logic matrix can be tested at least after the second metal layer has been deposited. For this purpose auxiliary pads are arranged on the storage chip. These pads can be arranged either on the periphery of the chip or in the kerf, so that no active chip area is lost. When the chip is tested by the auxiliary pads after the second metal layer has been deposited, a test protocol is prepared by a computer. This protocol indicates which of the chips tested have the required number of serviceable data channels and which data channel is defective.

In accordance with the parts number found serviceable, a third metal layer is subsequently personalized in such a manner that the serviceable data outputs required are invariably connected to the same, if necessary standardized, chip pads. For this purpose the known electron beam process is particularly suitable.

In addition to the advantage that only standard process steps need be carried out, there is the primary advantage that an extensive realtime test after the third metal...