Browse Prior Art Database

Dedicated Pin, Multiple Function Testing Circuit for LSI

IP.com Disclosure Number: IPCOM000086306D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Prilik, RJ: AUTHOR

Abstract

A dedicated pin, multiple function testing circuit is described for testing large-scale integration (LSI) circuits. A plurality of circuits are used to test a multiple pin device under test, one for each pin.

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Dedicated Pin, Multiple Function Testing Circuit for LSI

A dedicated pin, multiple function testing circuit is described for testing large- scale integration (LSI) circuits. A plurality of circuits are used to test a multiple pin device under test, one for each pin.

The figure shows TTL logic 1 which decodes address/data bus information and stores the program in registers, which serve as total on-card logic control.

The digital-to-analog converter (DAC) 2 acts as a programmable analog stimulus for the V/I (force voltage measure current-force current measure voltage) power supply 7, or a reference voltage for the functional detector 8.

A functional driver, consisting of 4 and 6 constitute a high-speed voltage or current pulse circuit for functional pattern testing, as disclosed in the IBM Technical Disclosure Bulletin, Vol. 18, No. 6, November 1975, pages 1930-1932.

The functional detector 8 compares device testing results from a device pin against an expected I/O value, and signals a pass or fail as latched/or realtime data.

System support circuits such as ground, high-voltage power supplies, or a picoammeter buss are available to the product under test pin via relay tree 9 and station A/B select 10, as well as all functions previously discussed, i.e., parametric V/I; functional driver; functional detector; or an open pin function if nothing is programmed to the product under test via 9 and 10.

Parametric measurement data 7 and/or functional test data 8 are avail...