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Programmable Logic Array using Charge Coupled Devices

IP.com Disclosure Number: IPCOM000086309D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+2]

Abstract

A programmable logic array (PLA) is described which employs charge-coupled devices to enable the programming thereof.

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Programmable Logic Array using Charge Coupled Devices

A programmable logic array (PLA) is described which employs charge- coupled devices to enable the programming thereof.

Fig. 1 illustrates the layout of the PLA showing the AND array of charged- coupled device cells 3 above, and the OR array of charge-coupled device cells 5 below, interconnected by the vertical metallized Y-select lines 2 and 4. Each Y- select line is connected by a via hole 14 to a Y electrode 10 composed of polycrystalline silicon within a oxide layer 22, Figs. 2a and 2b, in the AND array. In the OR array, each Y-select line is connected through a via hole to a X electrode composed of polycrystalline silicon.

Each charge-coupled device 3 in the AND array has an X electrode 12 composed of polycrystalline silicon, which is connected to horizontal polycrystalline silicon conductors 6 and 8 that extend across the array, the vertical metallized lines 2 and 4, as is shown to better advantage in Fig. 2. In the OR array, a Y electrode composed of polycrystalline silicon is connected to a horizontal polycrystalline silicon line.

By and beneath the electrode in each charge coupled device is a buried diffusion line 16 which serves to program the charge state of respective charge coupled devices 3.

The vertical metallized lines 2 and 4 are selectively connected to either ground potential or a drain potential. The horizontal polycrystalline silicon lines 6 in the AND array are selectively connected to either the output of the two-bit partitioning decoder or to ground potential. The horizontal polycrystalline silicon lines in the OR array are selectively connected to either ground potential or drain potential.

In operation, the charge-coupled device unit cells are used to store either a 1 or a 0 unit of binary information. A unit cell 15 is shown in Fig. 2. To enter a logical 0 into the cell 15, both the vertical metallized line 2 and the horizontal polycrystalline silicon line 6 are grounded, allowing any minority carriers previously stored within the charge-coupled device 15 to recombine. To write a logical 1 in a charge-coupled cell 15, use is made of the PN junction associated with the buried n+ diffusion 16 located beneath the deple...