Browse Prior Art Database

Interactive System for Testing Circuit

IP.com Disclosure Number: IPCOM000086322D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Berthe, JF: AUTHOR [+3]

Abstract

The drawing shows a test subject 2 such as a large-scale integrated circuit and components that test the subject. A simulator 3 is a program that is run on a digital processor and calculates the expected result from the test subject 2 for any particular test pattern. The test patterns are provided by a test pattern generator 4 which is also a program running on the processor. The test patterns are supplied to the simulator 3, and are also supplied to a tester 4 which provides test signals on a line 6 that are appropriate in timing and amplitude for operating the test subject.

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Interactive System for Testing Circuit

The drawing shows a test subject 2 such as a large-scale integrated circuit and components that test the subject. A simulator 3 is a program that is run on a digital processor and calculates the expected result from the test subject 2 for any particular test pattern. The test patterns are provided by a test pattern generator 4 which is also a program running on the processor. The test patterns are supplied to the simulator 3, and are also supplied to a tester 4 which provides test signals on a line 6 that are appropriate in timing and amplitude for operating the test subject.

The signals from the test subject 2 on a line 7 are converted by tester 5 to signals on a line 8 that are in a form to be used by other components of the test system. A compare operation 9, also performed by the processor, compares the expected result from simulator 3 with the actual test result from tester 5 and produces a signal on a line 10 when a fault has occurred. The components described so far are conventional in systems for testing circuit devices.

A display 12 is connected to the processor to receive the fault signal that is represented on line 10 and to receive a signal that is represented on line 11. The signal on line 11 is formed according to the operation of the simulator, and it shows on the display 12 a selected small portion of the circuit of the test subject 2 that is the subject of a particular test. The fault signal on line 10 can b...