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Accelerated Instruction Execution of BC JC Instructions

IP.com Disclosure Number: IPCOM000086337D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

Instruction handling in a stored program computer system is speeded up by eliminating unnecessary storage accesses during execution of branch and jump instruction, and thereby provides performance improvement. This speedup is achieved in a computer system where instructions are fetched a byte at a time

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Accelerated Instruction Execution of BC JC Instructions

Instruction handling in a stored program computer system is speeded up by eliminating unnecessary storage accesses during execution of branch and jump instruction, and thereby provides performance improvement. This speedup is achieved in a computer system where instructions are fetched a byte at a time

Indexed branch and jump on condition instructions, Figs. 1a and 1b, are each three-bytes long. The direct branch on condition instruction, Fig. 1c, is four-bytes long. Before fetching the third byte of the instructions in Figs. 1a and 1b and the third and fourth bytes of the instruction in Fig. 1c, the condition to be met is tested to determine if these bytes are really needed. If the bytes are not needed, the fetch thereof is avoided and the clock and addressing incrementing circuitry are properly controlled so that the next byte fetched is the first byte of the next sequential instruction in the instruction stream.

The instructions in the computer system partially shown in Fig. 2 are contained in storage 10. Instruction processing starts at I0 time. Clock times I0- II2 are provided by clock 30 under control of clock controls 35. The 0P code byte fetched during I0-I2 time is loaded into OP register 15. The Q byte is fetched during I3-I5 and entered into Q register 25. The Q byte contains the conditions under which a branch or jump will occur.

At I6 time, OP decode and condition logic 20 will have determined whether or not the branch or jump conditions have been met. If the conditions have been met, it is necessary to fetch the third byte (branch or jump displacement) for instructions of Figs. 1a and 1b or the third and fourth bytes (high and low branch addresses) sequentially for the instruction of Fig. 1c. For the instruction of Fig. 1a the branch displacement byte is entered into Y register 45 via Y gate 40, to be combined with the contents of index register 50 via X gate 55 and X register 60 by arithmetic and logic unit (ALU) 65, and the result is entered into instruction address register (IAR) 70 at I9 time.

The contents of IAR 70 prior to entering the result from ALU 65 had been incremented by 1 via X gate 55, X register 60 and ALU 65 during I...