Browse Prior Art Database

Demodulator With Bit Crowding Compensation

IP.com Disclosure Number: IPCOM000086353D
Original Publication Date: 1976-Aug-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Boothroyd, WA: AUTHOR

Abstract

This is a method for compensating for pulse crowding in a variable or fixed velocity decoding circuit or program.

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Demodulator With Bit Crowding Compensation

This is a method for compensating for pulse crowding in a variable or fixed velocity decoding circuit or program.

The method is based upon the creation of a register stack containing a table of transition to transition times, for evaluating the transition to transition time on both sides of the transition in question ("THIS" transition). (In an analog embodiment, sample and hold circuits would replace the registers.) When a condition which will cause crowding is found, then the stored transition to transition times that will be used in decoding future transitions are adjusted to move the crowded transition back to its nominal location. In double-frequency encoding, the transition sequences which will cause crowding are C-1 or 1-1-C: transitions which have unequal transition to transition space on opposite sides.

Referring to Fig. 1, the output of a F/2F read circuit is a series of pulses, labeled transitions T0 through T9. The times between transitions are designated L1-L5 (long transition times) and S1-S4 (short transition times). As each transition is observed (by timing circuitry, not shown), the time since the previously observed transition is computed and loaded into the C register of register stack 10, pushing the prior contents of the C register into the B register, and of the B register into the A register.

At this point, the B register contains the transition to transition time of the transition to be decoded (as a data or clock pulse), hereafter referred to as THIS transition; the C register contains the next transition to be evaluated (NEXT); and the A register, the last transition evaluated (LAST). The CC register 11 contains the transition to transition time of the last clock period evaluated.

Referring to Fig. 2, the method for evaluating and adjusting the contents of the A, B, C, and CC registers to decode the pulse train T0-T9 will be described. In this procedure, the pulse time contained in the B register is being evaluated to determine if, in F/2F code, it is a data 1 or 0 pulse, or a clock pulse not having data significance.

In step 20, power on reset resets to 0 the contents of the skip flag, and the A, B, C, and CC registers. In step 21, registers A, B, C, and CC are loaded with timing values derived from a series of leading clock pulses. Thereafter, in step 22, when a signal in the pulse train is detected as going on, such that the time elapsed since the previous transition has been computed and loaded into the C register, processing proceeds to step 23.

Here the skip flag is tested to determine whether or not THIS pulse is the second pulse of a short/short pair. If it is, the skip flag is turned off in step 34 and processing continues to step 35. If it is not, processing continues to step 24, where the B register is compared with the C register to recognize a potential need for long to short compensation, where a long transition is followed by a short transition.

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