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High Performance Interface between Memory Cells and Data Driver Circuit

IP.com Disclosure Number: IPCOM000086400D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Arzubi, LM: AUTHOR

Abstract

This circuit improves the performance of single field-effect transistors (FET)/capacitor memory array circuits. In such circuits it is difficult to provide fast propagation of data from the memory cells coupled to a bit line and to a data output driver. This is primarily due to the fact that the initially sensed data signal is single ended and because of the relatively large parasitic capacitance of data lines communicating with many bit lines.

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High Performance Interface between Memory Cells and Data Driver Circuit

This circuit improves the performance of single field-effect transistors (FET)/capacitor memory array circuits. In such circuits it is difficult to provide fast propagation of data from the memory cells coupled to a bit line and to a data output driver. This is primarily due to the fact that the initially sensed data signal is single ended and because of the relatively large parasitic capacitance of data lines communicating with many bit lines.

Increases in memory cell density and improvements in performance have led single-device cell FET memory array chips to be split into two or more arrays, each containing two sub-arrays having one row of sense latches. This splitting is normally done in an even number of arrays and only every other array is interrogated during selection.

The interface circuit consists of a differential data driver in which its input/output nodes are connected to each of the right and left Data Buses, which in turn communicate to the Right and Left Arrays, respectively. The differential data driver consists of a cross-coupled FET pair T1 and T2 with the proper precharge (PC) and set devices T3, T4 and T5 and two dummy cells (T7, C1 and T6, C2) which are cross-coupled to the signals that drive the bit switches T8 and T9.

In operation, after the sense latch in one of the arrays has been set, only one of the bit switches is powered in conjunction with the corresponding refer...