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Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000086441D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hansen, AA: AUTHOR

Abstract

The exclusive OR circuit is depicted in complementary field-effect transistor (FET) technology. Devices Q1, Q2 and Q7 are N-type FET's, while devices Q3, Q4, Q5 and Q6 are P-type FET's. The exclusive OR function is defined as: f(AB) = AB + AB.

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Exclusive OR Circuit

The exclusive OR circuit is depicted in complementary field-effect transistor (FET) technology. Devices Q1, Q2 and Q7 are N-type FET's, while devices Q3, Q4, Q5 and Q6 are P-type FET's. The exclusive OR function is defined as: f(AB) = AB + AB.

Pulses A and B are of amplitude VH with respect to VL. The transition from AB to AB will now be explained. When pulses AB are present, devices Q3 and Q4 are on, keeping node N1 at VH and Q1 and Q2 off. Node N1 is at potential VH, keeping devices Q7 on and Q6 off. The output node for the function f(AB) is, therefore, held to VL potential by Q7, rendering device Q5 on, also keeping node N1 at VH. During the transition pulse A to A from VL to VH, the gate to source voltage of devices Q1 reaches VGS >/= Absolute VG-VTH Absolute, turning Q1 on.

Current will flow from node N1 through device Q1, discharging node N1 to VGS >/= Absol. VG-VTH Absol., turning Q6 on. Simultaneously, the gate voltage of device Q7 decreases, turning device Q7 more off. When the amplitude of node N1 has discharged to VGS < Absol. VG-VTH Absol., device Q7 turns off. Current will now flow from VH through device Q6 charging the output voltage towards VGS >/= Absol. VG-VTH Absol. for device Q5, turning Q5 off. The output voltage will charge to VH.

The current path from VH through devices Q3 and Q4 is off because VGS = 0 for Q3.

The transition from :AB to :AB will now be explained. When pulses AB are at level VH, node N1 is at VH-VTH, henc...