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Two Phase Clock Pulse Generator having Fixed Phase Independent of Frequency

IP.com Disclosure Number: IPCOM000086444D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

Fig. 1 shows the two-phase clock pulse waveforms for operation of charge-coupled device and ratioless-type MOS shift registers. Such registers are often designed for operation over a wide frequency range so that the Phi 2 waveform delay relating to the Phi 1 waveform must be a constant amount independent of change in the frequency of the waveforms.

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Two Phase Clock Pulse Generator having Fixed Phase Independent of Frequency

Fig. 1 shows the two-phase clock pulse waveforms for operation of charge- coupled device and ratioless-type MOS shift registers. Such registers are often designed for operation over a wide frequency range so that the Phi 2 waveform delay relating to the Phi 1 waveform must be a constant amount independent of change in the frequency of the waveforms.

The circuit of Fig. 2 produces the required constant time delay between the variable frequency clock waveforms of Fig. 1. The input clock pulse waveform X is the master clock which has the same repetition rate as the data flow input to the register, not shown, being driven by the output Phi 1 and Phi 2 waveforms. Waveform Y is obtained by differentiating X by the respective RC circuit 1 and 2. Similarly, waveform Z is obtained by first inverting X using inverter 3 and then differentiating the inverted X pulses by the RC circuit 4 and 5. Fig. 3 shows the resulting waveforms Y and Z. Both RC circuits have the same time constant.

Pulses Y and Z are applied to NAND gate 6, producing output pulses A. Pulses A are coupled to J-K flip-flop 7, in turn providing output waveforms Q and
Q. Pulses A are also applied to OR gates 8 and 9, as are waveforms Q and Q, respectively. The desired clocking waveforms Phi 1 and Phi 2 are available at the outputs of the respective gates 8 and 9. The skew Delta t (defined as the time lapse between the leading edge of t...