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Browse Prior Art Database

Via Hole Formation in Quartz

IP.com Disclosure Number: IPCOM000086452D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Hayunga, PC: AUTHOR [+2]

Abstract

Via hole etching for zero overlap vias is a very important part of a high density multilayer metal structure for integrated circuits.

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Via Hole Formation in Quartz

Via hole etching for zero overlap vias is a very important part of a high density multilayer metal structure for integrated circuits.

When vias are opened through sputtered quartz layers, on semiconductor devices, it is very important that there be no tunneling at the bottom of the via hole, such as illustrated in Fig. 1. However, these tunneling effects are frequently encountered in present day planar quartz technology.

It has been found that in high-sputtered quartz step etching, the initial quartz deposited during the first few minutes (approx. 2 to 3 K Angstroms) was found to have a higher etch rate (Fig. 3). This indicates that quartz deposited at an early stage of sputtering had a higher deposition rate, was less dense and thus higher in porosity. Such structures on etching produce products such as shown in Fig. 1, illustrating the loose adhesion of quartz near the metal-substrate interface.

These tunneling effects can be avoided, as shown in Fig. 2, by first depositing quartz (approx. 2 to 3 K Angstroms) with a very high resputtering level to form a high density quartz. This is followed by deposition of the remaining quartz at normal levels employed in present technology to obtain planarity.

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