Browse Prior Art Database

Diffusion of Arsenic into Silicon from a Solid Phase

IP.com Disclosure Number: IPCOM000086453D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Sarma, VN: AUTHOR

Abstract

Fig. 1 shows a typical structure employed for diffusing arsenic (As) into a silicon substrate to establish diffused regions. The structure is prepared by forming a composite layer of an upper As doped glassy layer and an underlying thermal SiO(2) layer of approximately 700 Angstroms at the interface of the substrate and glassy layer. This is followed by heating the substrates and layers in an oxygen atmosphere to diffuse the As from the solid phase glassy layer through the SiO(2) layer into the substrate to the desired depth.

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Diffusion of Arsenic into Silicon from a Solid Phase

Fig. 1 shows a typical structure employed for diffusing arsenic (As) into a silicon substrate to establish diffused regions. The structure is prepared by forming a composite layer of an upper As doped glassy layer and an underlying thermal SiO(2) layer of approximately 700 Angstroms at the interface of the substrate and glassy layer. This is followed by heating the substrates and layers in an oxygen atmosphere to diffuse the As from the solid phase glassy layer through the SiO(2) layer into the substrate to the desired depth.

Although this process provides an effective means for fabrication of devices, improved yields are obtained by use of an intermediate thin layer, of approximately 250 Angstroms, of pyrolytic SiO(2) between the arsenic-doped glass and the thermally grown SiO(2), as illustrated in Fig. 2.

Post subcollector diffusion and post epitaxial etching (using preferential etching) of wafers showed a reduction of electrically active defects in the subcollector area. Such defects have been attributed to enhanced out-diffusion at these points to result in low collector breakdown and pipe-limited yields.

It has been postulated that such defects (in the structure of Fig. 1) are caused by reaction of silicon with the arsenic doped glass, which reached the substrate through pinholes in the thermal oxide, and thermal mismatch between the thermal oxide and the arsenic-doped glass with induced stress.

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