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Bipolar Programmed Logic Array Structure

IP.com Disclosure Number: IPCOM000086477D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+5]

Abstract

A bipolar programmed logic array (PLA) structure is proposed which promises better performance and higher density than FET-PLA's.

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Bipolar Programmed Logic Array Structure

A bipolar programmed logic array (PLA) structure is proposed which promises better performance and higher density than FET-PLA's.

This is achieved by using elements in the array and in the periphery, which fit each other perfectly. For the AND array, Schottky diodes are used, which can be disconnected from both the 'In Lines' and the 'Product Terms' (Fig. 1). This guarantees extremely low parasitic capacitance. For the OR array, NPN transistors, in an emitter follower configuration, are employed that can be implemented in a common N-bed. The NPN transistors can be disconnected from both the 'Product Terms' and the 'Out Lines'. There may be no amplifier stage between the AND array and the OR array. With these two array configurations, a very small cell size is achieved.

However, this small cell size can be utilized only with tight peripheral circuits. Therefore, merged transistor logic (MTL) circuits as decode circuits at the input (Fig. 2) and as latches at the output are suggested.

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