Browse Prior Art Database

Microprocessor Master Slice

IP.com Disclosure Number: IPCOM000086492D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Doughten, WL: AUTHOR [+2]

Abstract

A process is disclosed for making a one-cell memory master slice compatible with conventional FET logic layouts.

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Microprocessor Master Slice

A process is disclosed for making a one-cell memory master slice compatible with conventional FET logic layouts.

The process is divided into two stages, the first stage being the formation of the master slice one-cell memory elements and the second stage being the formation of conventional FET logic devices.

Figs. 1 thru 5 show the steps in the first stage of forming the master slice one-cell memory elements. Fig. 1 illustrates the silicon substrate 1 onto which has been deposited a silicon dioxide layer 2 followed by a photoresist layer 3, in which an opening has been made for the formation of the storage plate for the memory cell.

Fig. 2 illustrates the step where a trough 4 is formed in the semiconductor substrate to enable the storage plate to be formed at a level below the upper surface of the semiconductor wafer. Fig. 3 illustrates the diffusion of a lower plate electrode 6 and the formation of a thin oxide layer 5 for the memory element. Fig. 4 illustrates the deposition of the polycrystalline silicon layer 7 forming the upper electrode for the one-cell memory and the oxide insulating layer 8. Fig. 5 illustrates the final step of selectively etching away the peripheral portions of the polysilicon layer 7, leaving no polysilicon connecting line to the memory element.

The resulting wafer contains a master slice pattern of one-cell memory elements which may be selectively connected, to the balance of the logic circuit to be formed...