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Device Sharing in Array Logic

IP.com Disclosure Number: IPCOM000086508D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

A number of two dimensional, programmed logic arrays (PLA) are shown in which field-effect transistors (FET) are utilized. Following certain simple restrictions, FET-device sharing can be accomplished.

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Device Sharing in Array Logic

A number of two dimensional, programmed logic arrays (PLA) are shown in which field-effect transistors (FET) are utilized. Following certain simple restrictions, FET-device sharing can be accomplished.

In Fig. 1, inputs A and B are applied to a decoder 10 which energizes vertical lines in accordance with the logic functions shown. A normal implementation of a search or AND array would require an FET device 11 at each intersection of a vertical decoder output line and a output line 12. However, with two-bit partitioning, only 15 of the 16 possible states of a normal four-bit cell are generally useful. The unused state, that is all binary 1's in a particular row, is the only state that requires all four decoder 10 output lines. If this state is unused, then only three devices 11 are needed to implement any one of the 15 states represented on the output lines 12.

Fig. 2 shows a truth table for a two dimensional array, implemented as shown in Fig. 1, wherein the decoder 13 is a threshold-type decoder. That is, the outputs 14 are generated in various combinations reflecting whether or not there are 0, 1, 2, or 3 of the equal-weight inputs A, B and C present. The output of the array is represented at the right of Fig. 2. For example, the designation shown at 15, i.e., (A, B, C) 0, 1, 3, signifies that the output will be generated whenever there are exactly 0, 1, or 3 of the inputs A, B, or C present.

Fig. 3 is a truth-table representation...