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Integrated FET Latch Circuit

IP.com Disclosure Number: IPCOM000086525D
Original Publication Date: 1976-Sep-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Williams, RR: AUTHOR

Abstract

Latch 10 retains high operating speeds under heavier output loading than previous latches of its type. To achieve this result, two FETs, driven by a clock signal, are added between the outputs and the positive supply rail.

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Integrated FET Latch Circuit

Latch 10 retains high operating speeds under heavier output loading than previous latches of its type. To achieve this result, two FETs, driven by a clock signal, are added between the outputs and the positive supply rail.

Enhancement-mode field-effect transistors (FETs) 11 and 12 and depletion- mode FETs 13 and 14 form the bistable storage circuit of latch 10. To hold one side of this circuit at a valid "down" level in the steady state, FETs 11 and 12 must sink the current sourced from FETs 13 and 14, while maintaining a low drain-source voltage. For a given size of FETs 11 and 12, this fixes the size of FETs 13 and 14, and, thus, the power and the performance of latch 10.

To illustrate a switching operation of latch 10, assume that output 15 is high, output 16 is low, input 17 is low and input 18 is high. The leading edge of the next clock pulse on line 19 gates on enhancement-FETs 20-23. FET 21 aids FET 14 in supplying additional current, so as to charge the load capacitance of output 16 more rapidly. (No current is conducted from output 16 to ground, since FET 25 is assumed to be cut off.) Since output 15 is already at a high level, FET 20 does not conduct immediately. Thus, enhancement-FETs 22 and 24 pull this line toward ground to effect the switching of FETs 11 and 12.

If clock 19 and data input 18 remain high after latch 10 has completed switching, current supplied by FETs 13 and 20, in parallel is sunk by FETs 11, 22 and 24....