Browse Prior Art Database

Pulse Width Modulated DC/To/DC Converter

IP.com Disclosure Number: IPCOM000086595D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Bigbie, SE: AUTHOR [+2]

Abstract

The DC-to-DC converter provides a clock and ramp oscillator in one circuit, fault protection shut off, start-up circuit for soft turn on of outputs, and adjustable minimum and maximum pulse width.

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Pulse Width Modulated DC/To/DC Converter

The DC-to-DC converter provides a clock and ramp oscillator in one circuit, fault protection shut off, start-up circuit for soft turn on of outputs, and adjustable minimum and maximum pulse width.

Referring to Fig. 1, the DC/DC converter consists of high-voltage switching transistors Q9 and Q10 driving an output transformer T2. The drive for the switching transistors comes from a constant current transformer (interstage transformer T1) that forces the beta of the switching transistors. This interstage transformer is driven by Q4 and Q5. When both Q4 and Q5 are on, the primary of the interstage transformer is shorted and there is no drive to the switching transistors, thus providing variable dead time. When drive is needed, either Q4 or Q5 is turned off. After one-half cycle they both will be turned on again and then the opposite transistor turned off until the end of the full cycle.

Transistors Q1 and Q3 make up the oscillator that produces a linearly increasing ramp for the "-" input to comparator M4 and a clock pulse that is used to drive flip flop M1 to get the Q and Q clock outputs (Fig. 2). The clock is fed into Nand gates M2 and M3. The converter output voltage is sensed and compared to a reference voltage to give a varying DC level out of amplifier M5.

The ramp signal and the output of the amplifier are compared by M4 to give a varying pulse-width square-wave output. The output of the comparator M4, the clock Q and Q, and the start level are Nanded together by gates M2 and M3 to give a varying pulse-width modulated drive to Q4 and Q5, which in turn drive the main switches Q9 and Q10. In the above manner, the switching transistors are turned on and off to supply just enough drive to the output transformer to keep the output voltage at a predetermined level.

Transistors Q1, Q2 and Q3 and their associated resistors and capacitors make up a ramp and clock oscillator. Q1 is a constant current source set by P1 and R1 that charges C1 at a linear rate until VC1 gets to the pinch-off voltage VP of Q2. When the emitter of Q2 gets to VP, Q2 will turn on causing C1 to be discharged through the emitter-base junction to ground. This action will also produce a pulse on R4 that is used to change the state of flip flop M1. The ramp produced on C1 is buffered by Q3, leveled and shifted by C2 and fed into the "-" input of comparator M4. The timing chart (Fig. 2) shows the clock, clock not and ramp signals, and how they are related to the other parts of the control circuit.

This circuit differs from that shown in U. S. Patent 3,670,234 in that a ramp is used instead of a triangle wave and the ramp and clock come from the same circuit.

The converter incorporates a drive circuit that will turn the converter off when a "fault" is detected in the main power supply, thus protecting the converter from burning out. It also protects the loads and the supply drives. Nand gates M2 and M3 each have three inputs. T...