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Noise Eliminator Circuit

IP.com Disclosure Number: IPCOM000086597D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR

Abstract

This circuit, used in a current interface inhibits or eliminates current noise from a data line. The circuit uses a double integration of the input signal and, for the usual short-noise pulse, restores to its normal conduction condition at the end of the noise.

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Noise Eliminator Circuit

This circuit, used in a current interface inhibits or eliminates current noise from a data line. The circuit uses a double integration of the input signal and, for the usual short-noise pulse, restores to its normal conduction condition at the end of the noise.

Referring to Figs. 1 and 2, the incoming signal on line 1 provides an input at the base of the transistor 2, having a resistor 3 in its emitter circuit and acting as an emitter follower. The signal on its output line 4 (the second line of Fig. 2) is substantially the same as the input signal. Referring to Fig. 2, the presence of an unwanted noise pulse is indicated on the first line and it can also be seen on the second line. The signal on line 4 is applied to the gate of the P channel FET 5, having its drain connected to the midpoint 8 of the capacitor 7 and resistor 6. When the input and line 4 are down, FET 5 conducts and holds the node 8 at the positive level to keep capacitor 7 discharged. When the line 4 voltage becomes positive, FET 5 cuts off and capacitor 7 starts to discharge through resistor 6. This will occur during the noise pulse. However, as soon as the noise pulse is over, FET 5 again becomes conductive and the voltage at node 8 quickly returns to the positive voltage level, where it remains until line 4 becomes positive and capacitor 7 starts to discharge.

The FET 10, which has its gate connected to node 8 and its drain connected to the resistor 11, will be noncond...