Browse Prior Art Database

Storage Paging Device for Microcontrollers

IP.com Disclosure Number: IPCOM000086606D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Hanna, JT: AUTHOR [+4]

Abstract

This paging device far microcontrollers provides 12K bytes of storage. This is organized as pages 0, 1, 2 and 3 of read only store (ROS) 174, 176, 178 and 180. Also included are the direct-access storage device (DASD) 182 and basic ROS 184. Storage addresses 800 to FFF (SAR Bit 0 active) locate instructions in pages 0, 1, 2 and 3 and data in the DASD. The latter occurs only during a data cycle 114. Locations in pages 0-3 are accessed only during an instruction cycle 186. Storage addresses 00D-7FF (SAR phi inactive) locate instructions and data in basic store 184.

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Storage Paging Device for Microcontrollers

This paging device far microcontrollers provides 12K bytes of storage. This is organized as pages 0, 1, 2 and 3 of read only store (ROS) 174, 176, 178 and 180. Also included are the direct-access storage device (DASD) 182 and basic ROS 184. Storage addresses 800 to FFF (SAR Bit 0 active) locate instructions in pages 0, 1, 2 and 3 and data in the DASD. The latter occurs only during a data cycle 114. Locations in pages 0-3 are accessed only during an instruction cycle 186. Storage addresses 00D-7FF (SAR phi inactive) locate instructions and data in basic store 184.

The device provides 12K storage addressing capability with only 12 SAR (storage address) lines. The microcontroller data bus bit lines 100 and 102 are clocked into polarity-hold registers 120 and 122. Clocking is from the I/O address decode of AND circuit 116. The outputs of polarity hold latches 120 and 122 are then clocked into latches 128 and 130 at T phi time 110. T phi time is the first clock time of the microcontroller cycle. The outputs of polarity-hold latches 128 and 130 constitute the two page select bits on lines 132 and 134.

The two page select bits are decoded by the two-line to four-line decoder 136 into the four paging lines 144, 146, 148 and 150. These lines, in conjunction with the high order SAR line 112 (SAR phi) and instruction cycle on line 186, form page select lines 166, 168, 170 and 172. These lines are used to select instructions from RO...