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High Speed Test for Bank of 16 Four Bit Registers

IP.com Disclosure Number: IPCOM000086609D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 20K

Publishing Venue

IBM

Related People

Williams, DD: AUTHOR

Abstract

This routine could be used in a microcontroller to provide a fast test of a bank of 16 registers each having four bits. The routine is invoked prior to use by any program or if the register bank is not in use. This provides hardware-failure detection in a continuously running on-line program.

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High Speed Test for Bank of 16 Four Bit Registers

This routine could be used in a microcontroller to provide a fast test of a bank of 16 registers each having four bits. The routine is invoked prior to use by any program or if the register bank is not in use. This provides hardware-failure detection in a continuously running on-line program.

According to this method, the starting test pattern is first obtained. This may be a random number or any value that will contain a variable starting bit pattern. This value is stored in the first four-bit registers a. It is incremented by 1, and the incremented value is stored in the next register b. The value in register b is then incremented by 1, and this value is stored in the next register c. This process is continued until all of the 16 registers a-p have been loaded.

The final step is to add the contents of all 16 registers a-p together (ignoring carries), and test for a result equal to eight. If the result is not equal to eight, a register hardware failure has occurred, and appropriate action must be taken.

Continual execution of this routine, coupled with the variable starting bit pattern, will test all bit patterns in all of the 16 registers a-p, and will also test for register-addressing failures.

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