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Noise Rejection Timing Pulse Generation

IP.com Disclosure Number: IPCOM000086633D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hubbard, JH: AUTHOR [+2]

Abstract

Tachometer or emitter wheels are often used to time various machines, such as magnetic tape drives, transfer electrographic machines and milling machines. In general, a timing wheel is secured to the shaft of a motor M, which drives apparatus of diverse types. The timing wheel usually has a fiducial pulse location designated S and a series of timing pulses E either evenly or unevenly distributed around the periphery of the timing wheel. In accordance with the present arrangement, digital shift-register circuits provide noise rejection on the sensing of the synchronizing and timing pulses received from the timing wheel.

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Noise Rejection Timing Pulse Generation

Tachometer or emitter wheels are often used to time various machines, such as magnetic tape drives, transfer electrographic machines and milling machines. In general, a timing wheel is secured to the shaft of a motor M, which drives apparatus of diverse types. The timing wheel usually has a fiducial pulse location designated S and a series of timing pulses E either evenly or unevenly distributed around the periphery of the timing wheel. In accordance with the present arrangement, digital shift-register circuits provide noise rejection on the sensing of the synchronizing and timing pulses received from the timing wheel.

Referring to Fig. 1, both the fiducial and timing signals S and E are detected via digital shift-register circuits S' and E', respectively. A high frequency asynchronous clock supplies clock 1 and 2 signals over lines 1 and 2, respectively, to the shift registers. The first stage (SRX) of the two shift registers is timed by clock 1, as are all other odd-numbered stages (not shown), while the second and all other even-numbered stages are timed by clock 2. The arrangement of each shift register is such that a received E or S signal successively sets successive stages of the shift register through as many stages as desired, in accordance with the timing of clocks 1 and 2. As shown in the timing diagram of Fig. 3, three shift register stages are successively set for noise rejection. Stages SRD and SRE (not shown)...