Browse Prior Art Database

Memory Testing

IP.com Disclosure Number: IPCOM000086638D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Bappert, J: AUTHOR [+2]

Abstract

A memory having a 2/n/th unit (words or bytes) array services a digital computer via a data register. The computer selects the memory address word via an N-bit address register. For reliability purposes, it is desirable to verify the operation of the address register and its decoder (not shown) with respect to the memory array.

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Memory Testing

A memory having a 2/n/th unit (words or bytes) array services a digital computer via a data register. The computer selects the memory address word via an N-bit address register. For reliability purposes, it is desirable to verify the operation of the address register and its decoder (not shown) with respect to the memory array.

The test procedure includes storing any arbitrary character W1 or a combination of data signals in the all-zeroes address position. Memory address is then incremented by 1. A second character W2, other than the one initially selected, is stored at this memory address. The single-address bit is then left- shifted, with the second word being stored at each memory location, resulting in a pair of memory words being stored in a logical diagonal across the array. Finally, the first recorded word W1 is read out. If the addressing is correct, word W1 will not be altered. If incorrect, word W1 will be altered in accordance with the left-shifted single-address bit.

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