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Merged Transistor Logic Circuit With Majority Carrier Current Source

IP.com Disclosure Number: IPCOM000086643D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR [+3]

Abstract

By replacing the merged lateral PNP transistor with a field-effect transistor (FET) current source, the operating speed of a merged transistor logic circuit is enhanced.

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Merged Transistor Logic Circuit With Majority Carrier Current Source

By replacing the merged lateral PNP transistor with a field-effect transistor (FET) current source, the operating speed of a merged transistor logic circuit is enhanced.

Conventional merged transistor logic circuits are discussed in, e. g., IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 5, October 1974, pages 211-217, in an article entitled, "Terminal-Oriented Model for Merged Transistor Logic (MTL)" by H. H. Berger and S. K. Wiedmann. In the circuit shown in Fig. 1, a P- channel FET 10 is provided as a current source for transistors 12, 14, 16 and 18, arranged in parallel and having output terminals 01, 02, 03 and 04, respectively. An input signal is applied to this merged transistor logic circuit at terminal I.

Fig. 2 illustrates a specific embodiment of the circuit of Fig. 1 with a P- channel metal-oxide semiconductor field-effect transistor (MOSFET) 10' as the current source. MOSFET 10' includes a gate electrode 20 connected to a gate voltage terminal VG to which is applied a DC voltage of, e. g., -1.5 volts. A thin insulator 22, which may be made of silicon dioxide having a thickness preferably less than 500 angstroms, is interposed between the gate electrode 20 and the surface of the semiconductor substrate 24, which may have an N-type epitaxial layer. MOSFET 10' also includes a P-type diffusion, forming a current-carry electrode, to which is connected a voltage injection terminal Vi...