Browse Prior Art Database

Cross Coupled Sense Amplifier

IP.com Disclosure Number: IPCOM000086645D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Scribner, RN: AUTHOR

Abstract

In a cross-coupled parameter-insensitive sense amplifier, small positive, as well as negative, signals are detected. This circuit is very useful in detecting charge from a one-device memory cell, such as cell 10 or 12.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

Cross Coupled Sense Amplifier

In a cross-coupled parameter-insensitive sense amplifier, small positive, as well as negative, signals are detected. This circuit is very useful in detecting charge from a one-device memory cell, such as cell 10 or 12.

A basic sense amplifier insensitive to circuit parameters is described in U. S. Patent No. 3,764,906, and a cross-coupled sense amplifier described in U. S. Patent No. 3,760,381 employs the basic techniques of the amplifier disclosed in
U. S. Patent No. 3,764,906.

In this amplifier, both positive and negative signals, with respect to a precharged line voltage on the bit lines, are amplified by ensuring that field-effect transistors (FETs) T1 and T2 are turned off when input signals are first applied to nodes A and B, particularly when nodes A and B are coupled to large capacitive loads, such as those produced by bit-line capacitances Cb1 and Cb2.

In operation, FETs T3 and T4 are turned off, and nodes A and B are precharged to a voltage VI, turning on T1 and T2 and charging nodes C and D to a threshold voltage Vt, less than the gate voltage of T1 and T2, respectively, at which time T1 and T2 are turned off. With nodes A, B, C, and D precharged, as described, input signals, which may be derived from cell 10 or 12 as voltage VW is applied to the associated word line, are applied to nodes A and B when the voltage IA turns on FETs T5 and T6. Simultaneously, the voltage at P is increased sufficiently to insure that T1 and T2...