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Dynamic Memory Using a Dynamic Shift Register Sequencer

IP.com Disclosure Number: IPCOM000086646D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Harroun, TV: AUTHOR [+2]

Abstract

Volatile information stored in a dynamic memory array 10, such as those utilizing a single field-effect transistor (FET) to control the charge on a storage capacitor, is regenerated periodically by address pulses produced by an on-chip dynamic shift-register sequencer 12 which requires a minimum of semiconductor area, consumes very little power and preserves chip access and cycle performance.

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Dynamic Memory Using a Dynamic Shift Register Sequencer

Volatile information stored in a dynamic memory array 10, such as those utilizing a single field-effect transistor (FET) to control the charge on a storage capacitor, is regenerated periodically by address pulses produced by an on-chip dynamic shift-register sequencer 12 which requires a minimum of semiconductor area, consumes very little power and preserves chip access and cycle performance.

The sequencer 12 generates the entire set of word addresses, produced on lines A0 to A6 for a 128 word-line memory, which is comparable to the set of word addresses produced by a memory or storage-address register and applied to lines S0 to S6. The address lines S0 to S6 are connected to an address true/complement generator 14 which produces complementary pulses on a plurality of pairs of lines 0, 0 to 7, 7 when a chip-select pulse CS is applied to generator 14. The true/complement pulses are applied to a conventional word decoder 16 which selects the appropriate word drive line L0 to L127 for accessing the desired word in memory array 10.

In order to regenerate the information in memory array 10, a periodic pulse is applied to regeneration terminal 18 connected to a regeneration true/complement generator 20 which produces a true pulse REG at terminals A and a complement pulse REG at terminals B. The pulses REG and REG are applied to each of seven stages 22 to 34 of a linear shift-register generator of sequencer 12, whi...