Browse Prior Art Database

Memory System With High Performance Word Redundancy

IP.com Disclosure Number: IPCOM000086647D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Fitzgerald, BF: AUTHOR [+2]

Abstract

The system includes word redundancy circuitry providing little or no penalty in memory-access time by using separate sense amplifiers for the redundant word lines and selectively utilizing data read from the redundant word lines.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Memory System With High Performance Word Redundancy

The system includes word redundancy circuitry providing little or no penalty in memory-access time by using separate sense amplifiers for the redundant word lines and selectively utilizing data read from the redundant word lines.

The memory system receives word and bit memory or storage address register pulses which select a location in the memory array
10. The bit pulses are applied in a normal manner to bit decoder 11.

The word pulses are applied to both the word decoder 12 and the comparator 14. Word address pulses representative of defective word lines in the memory array 10 are stored in a defective address storage unit 16, such as a read-only memory which may utilize an appropriate blown fuse arrangement to provide the desired address. The storage unit 16 is connected to the comparator 14.

During normal operation the word memory address register pulses and pulses applied to comparator 14 from the defective address storage unit 16 do not match and, therefore, the redundant-word line 18, connected to the output of the comparator 14 through a redundant decoder 20, is not selected. The data in the selected location in the memory array is sensed by sense amplifiers 22 and applied to the data in/data out terminal through read/write buffer 24. Since the redundant word line 18 is not selected, the data-output control circuit 26 enables read/write buffer 24 but inhibits read/write buffer 28, which is connected to the output of...