Browse Prior Art Database

Multidefect Real Time Diagnosis Using Single Pin Probe

IP.com Disclosure Number: IPCOM000086658D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 6 page(s) / 90K

Publishing Venue

IBM

Related People

Zobniw, LM: AUTHOR

Abstract

This is a multidefect real-time diagnostic procedure that does not require fault simulation, which is costly with increased logic complexity. multidefect diagnosis may be required if the number of rework passes are limited. Multidefect diagnosis may improve diagnostic resolution. This multidefect real time (MRT) diagnostic algorithm makes real time deterministic decisions that direct a single-pin probe to as many nodes as are required to diagnose all "unrelated" (based on cause-effect) defects to the lowest repairable or replaceable units. In other words, each diagnosed defect need not be fixed before another defect on the assembly is diagnosed.

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Multidefect Real Time Diagnosis Using Single Pin Probe

This is a multidefect real-time diagnostic procedure that does not require fault simulation, which is costly with increased logic complexity. multidefect diagnosis may be required if the number of rework passes are limited. Multidefect diagnosis may improve diagnostic resolution. This multidefect real time (MRT) diagnostic algorithm makes real time deterministic decisions that direct a single-pin probe to as many nodes as are required to diagnose all "unrelated" (based on cause-effect) defects to the lowest repairable or replaceable units. In other words, each diagnosed defect need not be fixed before another defect on the assembly is diagnosed.

Required Data: Physical Model describes the assembly (e.g., printed circuit card) consisting of interconnected subassemblies (modules) and nets. The assembly has module and probe sides. The net includes all nodes that are physically interconnected and the interconnections. Nodes that affect the state of the net are called drivers. Nodes that are driven by the net are called sinks.

Resistors on the net are called terminators. Nodes (tabs) that are accessible for all testing are called primary pins (PIO), which include primary outputs (PO) and primary inputs (PI). Nodes that are accessible only if probed are called probe pins (PP). Net Dependency Data describes the interrelationship between the input nets (Inets) and dependent nets (Dnets). Inets control the state of Dnets. Come-From-Dependency data lists Inets per Dnet and logic circuitry between Inets and Dnet. Go-To-Dependency data lists Dnets per Inet. Logic Test consists of logic state (1, 0, X) tests. PIO and PP expected responses are referenced by test number of PI stimulus that caused them. PIO and PP are monitored after each stimulus. Test with smaller test number represents an earlier point in Logic Test. Tester monitors the Logic Test in logic steady-state mode, glitch mode, or both. Analog Voltage measurement is made at first encountered logic "1" and logic "0" state per PIO and per probed PP. Tester has the X-out capability per pin. X-out mechanism stores the pin's first failing test number, its failure, and Xes (don't care) all subsequent responses on the pin. Tester can perform resistance measurement tests between any physically monitored nodes (primary or internal). MRT ALGORITHM

MRT Algorithm's functions can be summarized as follows:

(1) Determine what node to probe.

(2) Apply Logic Test.

(3) Evaluate collected data to determine whether a defect

has been diagnosed or whether to continue probing.

(4) If a multidefect indication exists, then continue

probing, otherwise terminate.

Nonlogic Tests (block (BLK) 1 in figure) determines whether to apply Logic Test, whether a potential hazard exists to the operator tester, or AUT. Nonlogic tests include OPEN, SHORTS, and resistance

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(power off) tests, Testers power-on set-up tests. These tests are applied to primary...