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Switched Depletion Load Logic Circuit

IP.com Disclosure Number: IPCOM000086668D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Knepper, RW: AUTHOR

Abstract

This is an improved field-effect transistor (FET) circuit utilizing both enhancement and depletion (E/D) devices with a switched depletion-load device providing enhanced capacitive-load driving capabilities.

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Switched Depletion Load Logic Circuit

This is an improved field-effect transistor (FET) circuit utilizing both enhancement and depletion (E/D) devices with a switched depletion-load device providing enhanced capacitive-load driving capabilities.

The figure illustrates enhancement mode devices T4, T5, and T6 connected in a standard NOR logic circuit configuration with the capacitor CL illustrating the capacitive load. A pull-up circuit consisting of depletion-mode devices T1, T2, and T3 substantially improves the rise time and capacitive drive capability. A feedback arrangement from the output node through T3 causes node N1 to rise as soon as the output node begins to rise. Since node N1 is connected to the gate of T1, T1 is switched from a low-conduction state to a high-conduction state. The high conduction state of T1 provides rapid charging of the load capacitance. Devices T2 and T3 are, in essence, a switched transmission gate or a grounded- gate amplifier.

By turning all of transistors T4, T5, and T6 off, the output node begins to rise. At this time, T3 starts turning off. At a certain output-node voltage, T3 turns off completely allowing T2 to charge the gate of T1 quickly to the positive potential VH. In the downward transition, one of transistors T4, T5 or T6 conduct, causing T3 to turn on. This reduces the conduction of Tl, thereby limiting DC power. During the falling transition, T1 conducts a high current only momentarily until the output node (VOUT) dr...