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Read/Write Regeneration Arrangement for Bucket Brigade Shift Register

IP.com Disclosure Number: IPCOM000086713D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Aaron, RT: AUTHOR

Abstract

A resistive voltage-divider network is employed to improve the performance of a regenerative shift register.

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Read/Write Regeneration Arrangement for Bucket Brigade Shift Register

A resistive voltage-divider network is employed to improve the performance of a regenerative shift register.

A typical bucket-brigade shift register is depicted in Fig. 3. TA, TB and TC are N-channel field-effect transistors (FET). A voltage signal is transferred from node A to node B in accordance with input clocking signals BA and BB (Fig. 4). The resistor-divider network 11 (Fig. 1) provides the proper voltage levels for a logical "0", "1" and a reference potential midway between them to allow sensing. The logic "0" level (VO) is reduced by one threshold voltage (Vt) by transistor T1 as it feeds to the input capacitor C1 of the shift register. Thus, the level at C1 for a logic "0" is equal to (R4/(R1 + R2 + Ra + R4))VDD - Vt. In a similar manner, a logic "1" is equal to (R2 + R3 + R4)/(R1 + R2 Ra R4)VDB - Vt.

To write into the shift register, the write signal is brought to an up level. At phi D time, C-DIFF is precharged to VO (C-DIFF and C-1 are reset to ground at phi C time by T7). Device T2 holds the gate of T3 low during write time. If DATA IN is down, a logic "0" level is placed at C1. If DATA IN is up, T5 and T6 raise C- DIFF's potential to V1 at phi A time and a logic "1" is written in C1.

To read data, the shift register output is compared to a reference voltage (V REF) by the sense latch The dynamic off-chip driver (OCD) samples the sense latch inverter output at phi A time and pres...