Browse Prior Art Database

Method of Doubling Short Term Burst Memory Response Speed

IP.com Disclosure Number: IPCOM000086715D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Crabtree, EG: AUTHOR [+3]

Abstract

A method of doubling the short-term-burst memory response speed of a memory having alternate transparent refresh cycles includes monitoring the difference between the number of refresh cycles and the number of access cycles to indicate when an option is available to access the memory during both the refresh cycles and access cycles.

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Method of Doubling Short Term Burst Memory Response Speed

A method of doubling the short-term-burst memory response speed of a memory having alternate transparent refresh cycles includes monitoring the difference between the number of refresh cycles and the number of access cycles to indicate when an option is available to access the memory during both the refresh cycles and access cycles.

A memory is employed with an external system which has a chip-select signal (CS) down on alternate memory cycles (defined by the P2 pulse) so that the memory will perform refresh cycles or alternate memory cycles. There are applications when the system has a high memory demand for short term "burst" conditions. By modifying the system logic so that it monitors the difference (N) between the number of refresh cycles (number of times that CS is down when P2 is up) and the number of access cycles (number of times that CS is up when P2 is up) then anytime N is between zero and a maximum allowable number, it indicates to the system that there is an option to access the memory at double the normal speed without alternate refresh cycles until the N becomes zero. Then the system would operate at normal speed with alternate transparent refresh cycles.

Thus, a memory may be defined in which Nvm refresh cycles must be completed within a period Tvm and the normal cycle time of the external system is Tes which is twice as long as the memory cycle period Tm (Tes = 2Tm). If the external system did not reference the chip (CS down) for Nvm * 1/2 consecutive external system refresh (Tes period) then the system could operate at double speed (1/2 Tes period) for Nvm consecutive cycles before normal speed (Tes period) would be required.

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