Browse Prior Art Database

Multiple Partitioned Programmable Logic Array

IP.com Disclosure Number: IPCOM000086722D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Greenspan, SB: AUTHOR

Abstract

The programmable logic array (PLA) function can be significantly extended by (1) two-bit partitioning of AND array outputs and (2) double-level metal-wiring bus structures to partition any two AND array product terms prior to entering the OR array. Double-level metal also permits some of the product terms to pass directly into the OR array without any two-bit partitioning. An increase in product terms in the OR array may be attained by providing vertical metal lines as the input lines and horizontal diffusion lines as the output lines.

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Multiple Partitioned Programmable Logic Array

The programmable logic array (PLA) function can be significantly extended by (1) two-bit partitioning of AND array outputs and (2) double-level metal-wiring bus structures to partition any two AND array product terms prior to entering the OR array. Double-level metal also permits some of the product terms to pass directly into the OR array without any two-bit partitioning. An increase in product terms in the OR array may be attained by providing vertical metal lines as the input lines and horizontal diffusion lines as the output lines.

Fig. 1 shows a PLA with metal two-bit partitioning. A plurality of input variables A...J are provided on signal lines 21 to two-bit partitioning circuits
22...22/N/. The product terms from the partitioning circuits 22 are provided as inputs to a search/AND array 20 comprised of horizontal metal lines 23 and vertical diffused lines 24 which also serve as outputs from the array 20. FET devices (not shown) are appropriately located at the crosspoints of lines 23 and 24 and are personalized to be conductive or nonconductive by thin and thick oxide, respectively, to provide a prescribed output signal according to the input variables. A wiring bus 26 is connected to the diffused lines 24 to provide appropriate interconnections through a second plurality of two-bit partitioning circuits 28...28/N/.

Fig. 2 shows the wiring bus 26 in greater detail. It comprises a series of metal lines in approp...