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Digital Sensitivity Compensation Circuit for Optical Sensor

IP.com Disclosure Number: IPCOM000086725D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Biggle, JG: AUTHOR [+2]

Abstract

The performance of an optical sensor for detecting the passage of an object, e.g., a document, deteriorates with the passage of time through aging of components and accumulation of dust on the light source and the photosensitive device. Periodically the compensation circuit is activated to adjust the sensitivity of the sensor to account for changed circumstances.

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Digital Sensitivity Compensation Circuit for Optical Sensor

The performance of an optical sensor for detecting the passage of an object, e.g., a document, deteriorates with the passage of time through aging of components and accumulation of dust on the light source and the photosensitive device. Periodically the compensation circuit is activated to adjust the sensitivity of the sensor to account for changed circumstances.

Light-emitting diode (LED) light source current is constant and determined by resistor R1. PTX load resistance, and therefore PTX sensitivity, is increased in discrete steps by the control circuit. The control circuit comprises a three-bit counter and a switch. Upon application of the adjust signal FB (force black), the switch opens and the counter is reset thus shorting the PTX emitter to ground and connecting resistors R2, R3 and R4 to ground. The presence of the FB signal gates clock pulses to the counter. At count 4 the counter removes the short circuit; at count 5, R2 is disconnected from ground, at count 6, R3 is so disconnected and at count 7, R4.

The PTX output is buffered by transistor T, having series connected load resistances R6 and R7. The strobed voltage comparator (SVC) compares the output of T with a first threshold level TL0, established by resistors R8 and R9. Once the output of T exceeds TL0, the SVC output goes high, thus preventing further clock pulses from reaching the counter. Upon subsequent termination of the FB signal,...