Browse Prior Art Database

Latch for Data Store

IP.com Disclosure Number: IPCOM000086740D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Caprio, LA: AUTHOR [+2]

Abstract

The latch circuit of Fig. 1 responds to address signals on lines 2, 3 and 4, a CLOCK signal on line 5 and a data signal on line 6 to produce a DATA OUTPUT signal on line 7.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 97% of the total text.

Page 1 of 2

Latch for Data Store

The latch circuit of Fig. 1 responds to address signals on lines 2, 3 and 4, a CLOCK signal on line 5 and a data signal on line 6 to produce a DATA OUTPUT signal on line 7.

This circuit is one of a number of similar circuits, and it is enabled for a data output operation when a "1" logic level signal appears on an address line 2, 3 or
4. When it is addressed, one of the transistors of an OR Invert circuit 8 turns off to produce a NOT SELECT signal on line 11.

An invert circuit 12 receives the CLOCK signal on line 5 and produces a signal, NOT CLOCK, on line 13. An OR Invert circuit 15 receives the signals, NOT SELECT, on line 11 and NOT CLOCK, on line 13, and produces a signal, CLOCK AND SELECT on line 16. A circuit 17 receives the CHECK AND SELECT signal on line 16 and the CLOCK signal on line 5, and produces the AND Invert function of these signals on line 18. The clock component of the signal on line 16 is delayed with respect to the CLOCK signal on line 5 and the signals on lines 16 and 18 overlap, as Fig. 2 shows.

Transistors 20 and 21 form the AND Invert function of the signals on lines 16 and 18 at line 19. A transistor 22 inverts this signal to produce the DATA OUTPUT signal on line 7. Transistors 23 and 24 form the AND Invert function of DATA OUTPUT and NOT CLOCK on line 19. The overlap of signals on lines 16 and 18 is sufficient for this latching operation to occur before a change in the data at line 6.

1

Page 2 of 2

2

[This page con...