Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Supervisor Processor Subsystem

IP.com Disclosure Number: IPCOM000086745D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Johnson, EW: AUTHOR [+2]

Abstract

An arrangement is disclosed in a data processing system that improves performance on multiprocessing systems by providing those system functions that are global to the system in a separate processing unit termed the supervisor processor subsystem. This reduces the load on the central processing units, achieving a performance gain.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Supervisor Processor Subsystem

An arrangement is disclosed in a data processing system that improves performance on multiprocessing systems by providing those system functions that are global to the system in a separate processing unit termed the supervisor processor subsystem. This reduces the load on the central processing units, achieving a performance gain.

A current operating system (MVS) for multiprocessing systems uses the contents of main storage to control the interlocking of processing and to synchronize or serialize those functions requiring this. The use of storage in this fashion to serialize the use of resources that are by nature global to the system is not consistent with most central processing unit (CPU) designs since most of the CPU designs are optimized with local storage caches. These references necessary to serialize the use of global resources tend to be used serially by each processor and are not local, as is the normal storage used by a program.

A supervisor processor subsystem (SPS) is proposed to alleviate this problem. It will provide many of the functions that are at present implemented through main storage and are global to the system. By removing these functions from the central processor load, the performance of the system can be improved. The SPS also can provide improved algorithms for these functions since its performance is not as critical as the CPU. The system view of the SPS is shown in Figure 1. Depending on the function, the SPS can operate synchronously to the CPU or it can perform its function overlapped with the operation of the CPU.

The SPS consists of two primary hardware units, the instruction unit extension (IEX) and the supervisor processing unit (SPU). The IEX is logically part of each instruction unit of the CPU and there is one IEX for cach CPU. The SPU is global to the system and there is logically one of these in the system.

The IEX is the primary interface to the instruction processor (I-unit). When the I-unit decodes an instruction that is to be executed by the SPS, the instruction processor signals the IEX to execute the instruction. The IEX unit under control of the I-unit microcode will send a command to the SPU. The SPU will execute the command and send the results back to the IEX. When the results are received by the IEX, the IEX will complete the instruction. See Figure
2.

The SPU is logically divided into the partitioned array structure (PAS), the partitioned array control (PAC), and the common array support (CAS). See Figure 3.

The PAS contains the storage of the SPS. It consists of several different arrays which contain data for each of the functions implemented in the SPS. For each function implemented in the SPS there is a dedicated hardware requirement which is implemented in the PAC. Therefore, the PAC consists of several sets of hardware for each function implemented in the SPS. The CAS is a common unit that provides the control to insure that operations in the...