Browse Prior Art Database

Test Pattern Generator for Data Processing System

IP.com Disclosure Number: IPCOM000086747D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Goel, P: AUTHOR

Abstract

A circuit device can be tested by applying a pattern of signals to its input terminals and comparing the output signals of the device with the expected values. When a fault exists in the device, a point in the circuit is held at a "1" logic level or a "0" logic level without regard to the logic levels of the signals that are applied to the point. Test patterns are generated by a program that analyzes the connections between the input terminals and a particular component or group of components where a fault is to be detected. Not all test patterns that affect a resulting pattern of output signals might be attributable to a fault in some other component of the device being tested. Thus, a test pattern generator may operate through a number of trials before a test pattern is found that is satisfactory for a particular fault.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Test Pattern Generator for Data Processing System

A circuit device can be tested by applying a pattern of signals to its input terminals and comparing the output signals of the device with the expected values. When a fault exists in the device, a point in the circuit is held at a "1" logic level or a "0" logic level without regard to the logic levels of the signals that are applied to the point. Test patterns are generated by a program that analyzes the connections between the input terminals and a particular component or group of components where a fault is to be detected. Not all test patterns that affect a resulting pattern of output signals might be attributable to a fault in some other component of the device being tested. Thus, a test pattern generator may operate through a number of trials before a test pattern is found that is satisfactory for a particular fault.

The test pattern generator is controlled to make only a small number of tries for each fault. Under this limit, a test pattern generator can produce a satisfactory test pattern for most, but not necessarily all, faults. Then the test pattern generator operates on the remaining faults, if any, under the limitation that the test generator continues only so long as, at least, one additional test is generated during each of a sequence of timed intervals. It has been found that further test generation on the remaining faults would not produce significantly more useful test patterns.

1