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Delay Test Generation Using Longest/Shortest Delay Paths

IP.com Disclosure Number: IPCOM000086749D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Hsieh, EP: AUTHOR

Abstract

Delay testing is a new form of testing designed to screen large scale integration (LSI) products from defects that cause excessive delays on signal paths on the package. The product delay testing strategy set forth requires delay testing on every block input and/or output on the product in both directions of transitions in its longest and shortest sensitizable delay path. An optimal algorithm is proposed to generate delay tests according to the product delay testing strategy.

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Delay Test Generation Using Longest/Shortest Delay Paths

Delay testing is a new form of testing designed to screen large scale integration (LSI) products from defects that cause excessive delays on signal paths on the package. The product delay testing strategy set forth requires delay testing on every block input and/or output on the product in both directions of transitions in its longest and shortest sensitizable delay path. An optimal algorithm is proposed to generate delay tests according to the product delay testing strategy.

A set of delay tests is applied in performing delay testing. A delay test initiates a transition from a controllable input of the LSI package, sets up package primary input (PI) conditions to propagate the transition to a target observable output, and observe the test result at the target by a clock pulse or strobe applied at a precalculated time instant. Thus a set of delay tests, when applied to a high- performance LSI product, can ensure that the delay of transition paths associated with the delay tests do not exceed a set of prespecified upper limits in the product under test.

Since the number of paths existing on a dense LSI product is extremely large (grows exponentially as the number of logic levels), it is not feasible to perform delay testing exhaustively on all paths on the product. A good strategy is to delay test every block input and/or output on the product in both directions of transition in its longest and shortest sensitizable delay paths. The next longest (shortest) delay path should be tested if no longer (shorter) delay path can be delay tested due to logical configurations.

The generation of a delay test for a given block can best be described in the following three stages: 1. Forward Sensitization

Starting from the specified block (called B.U.T. for block

under test), sensitize the longest/shortest delay path

leading to a TARGET observable output to propagate a

transition initiated at the B.U.T.

2. Backward Sensitization

Starting from the B.U.T., sensitize the longest/shortest

delay path backtraced to a controllable input, called the

SOURCE, such that a transition placed on the SOURCE

controllable input will cause a transition at the B.U.T.

3. Justification

Justify any and all internal net values required for

forward and backward sensitization to controllable

inputs.

This test generation technique uses two tables to guide the selection of the longest/shortest delay path during test generation, the Maximum Come From Weight (MCFW) table and the Maximum Go To Weight (MGTW) table. The MCFW table has one entry for each Come From (CF) of each block in t...