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FET Signal Receiver for VTL Circuits

IP.com Disclosure Number: IPCOM000086751D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR

Abstract

In translating signals received from vendor's transistor logic (VTL) circuits, in transistor-transistor logic (TTL), into signals for operating field-effect transistor (FET) circuits, earlier circuits have been slow and unreliable. This is because the guaranteed voltage swing of a VTL module is only one volt, from about one-half volt to one-and-one-half volts, and the higher limit is close to the conducting threshold of an FET.

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FET Signal Receiver for VTL Circuits

In translating signals received from vendor's transistor logic (VTL) circuits, in transistor-transistor logic (TTL), into signals for operating field-effect transistor (FET) circuits, earlier circuits have been slow and unreliable. This is because the guaranteed voltage swing of a VTL module is only one volt, from about one-half volt to one-and-one-half volts, and the higher limit is close to the conducting threshold of an FET.

The circuit shown above will translate VTL input signals into much wider range signals, wherein the delay and driving characteristics are much improved. As shown, an enhanced FET 1 has its gate connected to a source 2 of input signals. The drain of FET 1 is connected through a depleted FET 3 to a positive voltage source.

The gate of FET 3 is connected to its source. FETs 1 and 3 are paralleled by another pair of similar FETs 4 and 5 in which the gate of FET 4 is connected to a reference voltage approximately midway between the on-off levels of input 2. The reference voltage on the gate of FET 4 is generated by a pair of depleted type FETs 6 and 7 connected in series between the voltage source +V and a ground level. The gates of both FETs 6 and 7 are connected together and to their common node to maintain the reference voltage on lead 8. For VTLs this will be at about one volt, but a different level can be set by proportioning the parameters of FETs 6 and 7.

The sources of FETs 1 and 4 are connected to the drain of a depleted FET 10, having its gate and source conne...