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Diagnostic Error Forcing Circuit

IP.com Disclosure Number: IPCOM000086753D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Cooper, RJ: AUTHOR [+3]

Abstract

The above circuit is a diagnostic aid to insure that the error checking and correction circuits of a field-effect transistor (FET) memory are operative. The usual FET memory, with an error checking and correcting circuit, comprises an FET memory 1 which will store words large enough to hold all of the data bits of a word plus a group of check bits, here shown as 16 data and 6 check bits. The data bits will be received from a central control unit (CCU) 2 over a bus 3. The data bits are also received by an ECC generator 4 which generates the 6 check bits for the data and puts them on a bus 5 to memory 1 for storage with the data on bus 3. Each check bit is generated as an odd-parity bit for a group of 8 of the 16 data bits on bus 3, with each data bit position appearing in three of the six groups.

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Diagnostic Error Forcing Circuit

The above circuit is a diagnostic aid to insure that the error checking and correction circuits of a field-effect transistor (FET) memory are operative. The usual FET memory, with an error checking and correcting circuit, comprises an FET memory 1 which will store words large enough to hold all of the data bits of a word plus a group of check bits, here shown as 16 data and 6 check bits. The data bits will be received from a central control unit (CCU) 2 over a bus 3. The data bits are also received by an ECC generator 4 which generates the 6 check bits for the data and puts them on a bus 5 to memory 1 for storage with the data on bus 3. Each check bit is generated as an odd-parity bit for a group of 8 of the 16 data bits on bus 3, with each data bit position appearing in three of the six groups.

When the data word is read from memory 1, the 16 data and 6 check bits are received by an ECC decoder 6 which will regenerate 6 check bits from the data bits, check them with the original check bits from memory 1 and correct any data bits found to be in error. Decoder 6 will then send the corrected data bits and two generated parity bits on a bus 7 to control unit 2. A double-bit error cannot be corrected, but the CCU 2 will be notified in such an event.

When it is desired to test the decoder 6 and generator 4 for correct operation, the CCU 2 can be used to introduce errors to determine if they are corrected. For this introduction, a diagn...