Browse Prior Art Database

Logic Controlled Power Switch for Controlling Circuits

IP.com Disclosure Number: IPCOM000086766D
Original Publication Date: 1976-Oct-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Nielsen, DE: AUTHOR

Abstract

This circuit arrangement reduces the average chip power dissipation by disabling circuitry on the chip, normally consuming power, when not functioning.

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Logic Controlled Power Switch for Controlling Circuits

This circuit arrangement reduces the average chip power dissipation by disabling circuitry on the chip, normally consuming power, when not functioning.

The circuitry on a semiconductor chip is divided into at least two groups functioning alternately. Substantially large amounts of power are drawn by each of the two groups. The example shows but one of many circuits for each group made up of many identical NOR circuits on the chip comprising a large multiple of N-channel field-effect transistor (FET) devices.

Power is supplied to a clock-gating circuit 12 and a large number of other circuits functioning at the same time by applying a negative voltage level between control terminals 14 and 16. This turns a normally conducting FET device 18 off and applies a positive voltage to the gates of the enhancement- mode FET devices 20, 22 and 24. Logic levels at terminals 32, 34 and 36 now control the functioning of FET devices 38, 40, 42, 44, 46 and 48, resulting in a gated clock at terminals 50 and 52. Other circuits in this group are similarly powered.

On removing the negative voltage level and applying a relatively positive voltage level at the control terminals 14 and 16, an FET device 54 with an enhancement-mode FET device 56 in the same chip acts as an inverting circuit and turns off the normally conducting FET device 58. Energizing voltage is then applied to enhancement-mode FET devices 60, 62 and 64. Logic leve...